This one also have RISCV32 MCUs, runs linux. but for $89 its getting good
This seems to be quite powerful SBC, comes neck to neck with rpi4, but now we have rpi5
Here is a good list of all riscv based hardware
As I was hoping for long, RPI PICO series has picked up RISC-V as well, right now they are offerred as option to choose from ARM M33 or RV32 cores, Its a good way to introduce new architecture. I still think not having Zephyr as first class RTOS on Pico is a bit of let down. They still bet on FreeRTOS, and I am saying zephyr has won the RTOS battle, get in line
https://www.raspberrypi.com/news/raspberry-pi-pico-2-our-new-5-microcontroller-board-on-sale-now/
A little more information on the Risc-V support in this device:
Although we’ve been a member of RISC-V International for many years, we’ve never found an opportunity to ship a RISC-V Raspberry Pi product. But that’s changing today, thanks to a bonus feature of RP2350: a pair of open-hardware Hazard3 RISC-V cores which can be substituted at boot time for the Cortex-M33 cores. Our boot ROM can even auto-detect the architecture for which a second-stage binary has been built and reboot the chip into the appropriate mode. All features of the chip, apart from a handful of security features, and the double-precision floating-point accelerator, are available in RISC-V mode.
Hazard3 was developed by Luke Wren, currently a Principal Engineer in the Raspberry Pi chip team, in his free time. As a solo project, it’s an intellectual tour de force: a highly optimised three-stage pipelined processor, implementing the RV32I instruction set, and a large collection of standard extensions targeting performance and code density. If you’d like to know more, I recommend a browse through Luke’s historical posts on Twitter/X, which cover the development process in considerable detail.
In adding Hazard3 to RP2350, we’re aiming to give software developers a chance to experiment with the RISC-V architecture in a stable, well-supported environment, and to popularize Hazard3 as a clean, open core, suitable for verbatim use in other devices, or as a basis for further development.
Looks like some pretty amazing engineering: